During test and assembly operations, semiconductor devices are subject to large amounts of mechanical and thermal stresses. This is particularly true of devices with increasingly finer feature sizes, as the propensity for intra- and inter-level shorts caused by such operations drastically increases. Devices that have been diced, tested and assembled in packages often show signs of stress-related failures. These may be small microscopic cracks or highly visible stress-relief mechanisms such as film delamination, buckling, cracking, etc. In such cases, devices damage and attendant loss of useful life, leads to increased replacement costs. Moreover, these cracks and deformation-induced defects are difficult to detect, requiring large amounts of exhaustive failure analyses.